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78Q2120 10/100base - tx ethernet transceiver april 2000 description the 78Q2120 is a 10base - t/100base - tx fast ethernet transceiver. it includes integrated mii, endecs, scrambler/descrambler, dual - speed clock recovery, and full - featured auto - negotiation functions. the transmitter includes an on - chip pulse - shaper and a low - power line driver. the receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. the transceiver interfaces to cate gory - 5 unshielded twisted pair (cat - 5 utp) cabling, and is connected to the line media via 1:1 isolation transformers. no external filter is required. interface to the mac is accomplished through an ieee - 802.3 compliant media independent interface (mii). t he product is fabricated in a bicmos process for high performance and low power operation, and can operate from a single 3.3 v or 5 v supply. features 10base - t/100base - tx ieee - 802.3 compliant tx and rx functions requiring a dual 1:1 isolation transformer interface to the line integrated mii, 10base - t/100base - tx endec, 100base - tx scrambler/descrambler, and full - featured auto - negotiation function full duplex operation capable pcs bypass supports 5 - bit symbol interface dual speed clock recovery automatic po larity correction during auto - negotiation and 10base - t signal reception power - saving and power - down modes including transmitter disable bicmos technology, operates with a single 3.3v or 5v supply led indicators: link,tx,rx,col,100,10,fdx user programmable interrupt pin general purpose i/o interface (80 - pin package only) 64 and 80 - lead tqfp (jedec lqfp), 64 - pin qfp packages block diagram mii serial management & control transmit adaptive eq, baseline wander corrector, mlt3 decoder, nrzi/nrz 4b/5b encoder, scrambler, parallel/serial mii registers & interface logic parallel/serial, manchester encoder manchester decoder, serial/parallel serial/parallel, descrambler, 5b/4b decoder nrz/nrzi, mtl3 encoder pulse shaper & filter tx clock generator carrier sense, collision detect auto negotiation clock recovery clock reference utp drivers utp receiver leds vcc ground rxip rxin txop txon link tx rx col 100bt 10bt fdx 100m 100m 10m 10m receive ckin
78Q2120 10/100base - tx ethernet transceiver 2 functional descripti on general supply voltage the 78Q2120 can operate from either a single 3.3v ( 0.3v) or 5.0v ( 0.5v) power supply. the chip automatically adapts to the supply voltage used. no pin configuration is required. power management the 78Q2120 has three power saving modes: chip power - down recei ve power management transmit high impedance mode chip power - down is activated by setting the pwrdn bit in the mii register (mr0.11) or pulling high the pwrdn pin. when the chip is in power - down mode, all on - chip circuitry is shut off, and the device consum es minimum power. while in power - down state, the 78Q2120 still responds to management transactions. receive power management (rxcc mode) is activated by setting the rxcc bit in the mii register (mr16.0). in this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (pll), and all other receive circuitry will be powered down when no valid signal is present at the utp receive line interface. as soon as a valid signal is detected, all circuits will automatically be powered up to resum e normal operation. during this mode of operation, rx_clk will be inactive when there is no data being received. note that the rxcc mode is not supported during 10base - t operation. transmit high impedance mode is activated by setting the txhim bit in the mii register (mr16.12). in this mode of operation, the transmit utp drivers are in a high impedance state and txclk is tri - stated. a weak internal pull - up is enabled on txclk. the receive circuitry remains fully operational. the default state of mr16.12 i s a logic low for disabling the transmit high impedance mode. only a reset condition will automatically clear mr16.12. the transmitter is fully functional when mr16.12 is cleared. analog biasing the 78Q2120 uses the reference clock and an external resistor to generate accurate bias voltages for the chip. clock selection the 78Q2120 will default to use the on - chip crystal oscillator. in this mode a 25mhz crystal is connected between the xtlp and xtln pins. the ckin pin should be tied low. alternatively, an externally generated 25mhz clock can be connected to the ckin pin. the chip senses activity on the ckin pin, and will automatically configure itself to use the external clock. in this mode of operation, a crystal is not required and the xtlp and xtln pi ns should be connected together. transmit clock gener ation the transmitter uses an on - chip frequency synthesizer to generate the transmit clock. in 100base - tx operation, the synthesizer multiplies the reference clock by 5 to obtain the internal 125mhz seri al transmit clock. in 10base - t mode, it generates an internal 20mhz transmit clock by multiplying the reference 25mhz clock by 4/5. the synthesizer references either the local 25 mhz crystal oscillator, or the externally applied clock, depending on the se lected mode of operation . receive signal quali fication the integrated signal qualifier has separate squelch and un - squelch thresholds, and includes a built - in timer to ensure fast and accurate signal detection and receive noise rejection. upon detection o f two or more valid 10base - t or 100base - tx pulses on the line receive port, the pass indication, indicating the presence of valid receive signals or data, will be asserted. when pass is asserted, the signal detect threshold is lowered by about 60%, and al l adaptive circuits are released from their quiescent operating conditions, allowing them to lock onto the incoming data. in 100base - tx operation, pass will be de - asserted when no signal is presented for a period of about 1.2us. in 10base - t operation, pas s will be de - asserted whenever no manchester data is received. in either case, the signal detect threshold will return to the squelched level whenever the pass indication is de - asserted. the pass signal is used internally to control the operation of the r eceive clock recovery. receive clock recove ry in 100base - tx mode, the 125mhz receive clock is extracted using a narrow - band pll. when no receive signal is present, the pll is directed to lock onto the transmit 125 mhz clock. when pass is asserted, the pll will use the received nrzi signal as the clock reference. the recovered clock is used to re - time the data signal and for conversion of the data to nrz format. in 10base - t mode, the 10mhz clock is recovered using a pll. for fast acquisition, the receive p ll is locked onto the transmit reference clock during idle receive periods. when manchester - coded preambles are detected, the pll adjusts its phase and re - synchronizes with the incoming manchester data.
78Q2120 10/100base - tx ethernet transceiver 3 100base - tx operation 100base - tx transmit the 78Q2120 contains all of the necessary circuitry to convert the transmit mii signaling from a mac to an ieee - 802.3 compliant data - stream driving cat - 5 utp cabling. the internal pcs interface maps 4 bit nibbles from the mii to 5 bit code groups as defined in table 24 - 1 of ieee - 802.3. these 5 bit code groups are then scrambled and converted to a serial stream before being sent to the mlt - 3 pulse shaping circuitry and line driver. the pulse - shaper uses current modulation to produce the desired output waveform. cont rolled rise/fall time in mlt - 3 signal is achieved using an accurately controlled c/i filter. the line driver requires an external 1:1 isolation transformer to interface with the line media. the center - tap of the primary side of the transformer should be connected to vcc. 100base - tx receive the 78Q2120 receives a 125mbaud mlt - 3 signal through a 1:1 transformer. the signal then goes through a combination of adaptive offset adjustment (baseline wander correction) and adaptive equalization. the effect of th ese circuits is to sense the amount of dispersion and attenuation caused by the cable and transformer, and restore the received pulses to logic levels. the amount of gain and equalization applied to the pulses varies with the detected attenuation and disp ersion and, therefore, with the length of the cable. the 78Q2120 can recover up to a 10db of loss in signal amplitude at 16 mhz. this loss is represented as test - chan 5 in annexa of the ansi x3.263:199x specification and corresponds to approximately 140m of cat5 utp cabling. the equalized mlt - 3 data signal is sliced and the resulting bit - stream is presented to the clock recovery pll and to a serial to parallel converter. the parallel data from the converter is then descrambled and aligned into 5 bit cod e groups. the receive pcs interface maps these code groups to 4 bit data for the mii as outlined in table 24 - 1 in clause 24 of ieee - 802.3 pcs bypass mode the pcs bypass mode is entered by pulling pcsbp high or by setting register bit mr 16.1. in this mod e the 78Q2120 accepts scrambled 5 bit code into the pins tx_er and txd[3:0]. tx_er is the msb data input. the 5 bit code groups are converted to an mlt - 3 signal. the received mlt - 3 signal is converted to 5 bit nrz code groups and output from the rx_er a nd rxd[3:0] pins. the rx_er pin is the msb data output. the rx_dv and tx_en pins are unused in pcs bypass mode. 10base - t operation 10base - t transmit the 78Q2120 takes 4 bit parallel nrz data via the mii interface and passes it through a parallel to seria l converter. the data is then passed through a manchester encoder and then on to the twisted pair pulse shaping circuitry and the twisted pair drive circuitry. an advanced pulse shaper employs a gm - c filter to pre - distort the output waveform to meet the output voltage template and spectral content requirements detailed in clause 14 of ieee - 802.3. interface to the twisted pair media is through two external 50 ohm resistors and a center - tapped 1:1 transformer; no external filtering is required. during auto - negotiation and during 10base - t idle periods, link pulses are transmitted. the 78Q2120 employs an onboard timer to prevent the mac from capturing a network through excessively long transmissions. when this timer is exceeded the chip enters the jabber s tate, and transmission is disabled. the jabber state is exited after the mii goes idle for 500ms 250ms. 10base - t receive the 78Q2120 receives manchester encoded 10base - t data through the twisted pair inputs and re - establishes logic levels through a slic er with a smart squelch function. the slicer automatically adjusts its level after valid data with the appropriate levels are detected. data is passed on to the 10base - t pll where the clock is recovered, data is re - timed and passed through a manchester d ecoder. from here data enters the serial to parallel converter for transmission to the mac via the media independent interface. interface to the twisted pair media is through an external 100 ohm resistor and a 1:1 center - tapped transformer; no external fi ltering is required. polarity information is detected and corrected in the internal circuitry. polarity correction the 78Q2120 is capable of either automatic or manual polarity reversal for 10base - t and auto - negotiation. these features are controlled b y register bits mr16.5 and mr16.4. the default is automatic mode where mr16.5 is low and mr16.4 indicates if the detection circuitry has inverted the input signal. to enter manual mode, mr16.5 is set high and mr16.4 will then control the signal polarity.
78Q2120 10/100base - tx ethernet transceiver 4 sqe test the 78Q2120 supports the signal quality error (sqe) function detailed in ieee - 802.3. at an interval of 1 m s after each negative transition of the txen pin in 10base - t mode, the col pin will go high for a period of 1 m s. this function can be disabled through register bit mr16.11. natural loopback when the 78Q2120 is transmitting and not receiving on the twisted pair media, data on the txd pins is looped back onto the rxd pins. during a collision, data from the rxi pins is routed to the rxd pins. the natural loopback function can be enabled through register bit mr16.10. repeater mode when the rptr pin is high or register bit mr 16.15 is set the 78Q2120 is placed in repeater mode. in this mode, full duplex operation is prohibited, crs responds only to receive activity and, in 10base - t mode, the sqe test function is disabled. auto - negotiation the 78Q2120 supports the auto - negotiation functions of clause 28 of ieee - 802.3. this function can b e enabled via a pin strap to the device or through registers. if the anega pin is tied high, the auto - negotiation function defaults to on and bit mr0.12, anegen, is high after reset. software can disable the auto - negotiation function by writing to bit mr 0.12 if the anega pin is tied low the function defaults to off and bit mr0.12 is set low after reset and cannot be written to. the contents of register mr4 are sent to the 78Q2120?s link partner during auto - negotiation, coded in fast link pulses. bits m r4.8:5 reflect the state of the tech[2:0] pins after reset. if tech[2:0] = 111, then all 4 bits are high. if tech[2:0] = 001, then only bit 5 is high. after reset, software can change any of these bits from a 1 to a 0; but not from a 0 to a 1. therefor e, a technology permitted by the setting of the tech pins can be disabled, but one not permitted cannot be enabled. with auto - negotiation enabled, the 78Q2120 will start sending fast link pulses at power on, loss of link or a command to restart. at the sa me time it will look for either 10base - t idle, 100base - tx idle or fast link pulses from its link partner. if either idle pattern is detected, the 78Q2120 configures itself in half - duplex mode at the appropriate speed. if it detects fast link pulses, it d ecodes and analyzes the link code transmitted by the link partner. when three identical link code words are received (ignoring the acknowledge bit) the link code word is stored in register 5. upon receiving three more identical link code words, with the a cknowledge bit set, the 78Q2120 configures itself to the highest priority technology common to the two link partners. the technology priorities are, in descending order: 100base - tx, full duplex 100base - tx, half duplex 10base - t, full duplex 10base - t, half d uplex once auto - negotiation is complete, register bits mr18.11:10 will reflect the actual speed and duplex that was chosen. if auto - negotiation fails to establish a link for any reason, register bit mr18.12 will reflect this and auto negotiation will resta rt from the beginning. writing a one to bit mr0.9, raneg, will also cause auto - negotiation to restart. media independent in terface mii transmit and receive operation the mii interface on the 78Q2120 provides independent transmit and receive paths for both 10mb/s and 100mb/s data rates as described in clause 22 of the ieee - 802.3 standard. the transmit clock, tx_clk, provides the timing reference for the transfer of tx_en, txd[3:0], and tx_er signals from the mac to the 78Q2120. txd[3:0] is captured on t he rising edge of tx_clk when tx_en is asserted. tx_er is also captured on the rising edge of tx_clk and is asserted by the mac to request that an error code group be transmitted. the assertion of tx_er has no affect when the 78Q2120 is operating in 10ba se - t mode. the receive clock, rx_clk, provides the timing reference to transfer rx_dv, rxd[3:0], and rx_er signals from the 78Q2120 to the mac. rx_dv transitions synchronously with respect to rx_clk and is asserted when the 78Q2120 is presenting valid da ta on rxd[3:0]. rx_er is asserted when a code group violation has been detected in the current receive packet and is also synchronous to rx_clk. station management i nterface the station management interface consists of circuitry which implements the seria l protocol as described in clause 22.2.4.4 of ieee - 802.3. a 16 - bit shift register receives serial data applied to the
78Q2120 10/100base - tx ethernet transceiver 5 mdio pin at the rising edge of the mdc clock signal. once the preamble is received, the station management control logic looks for the sta rt - of - frame sequence and a read or write op - code, followed by the phyad and regad fields. for a read operation, the mdio port becomes enabled as an output and the register data is loaded into a shift register for transmission. the 78Q2120 can work with a one bit preamble rather than the 32 bits proscribed by ieee - 802.3. this allows for faster programming of the registers. if a register does not exist at an address indicated by the regad field or if the phyad field does not match the 78Q2120 phyad indica ted by the phyad pins, a read of the mdio port will return all ones. for a write operation, the data is shifted in and loaded into the appropriate register after the sixteenth data bit has been received. writes to registers not supported by the 78Q2120 are ignored. when the phyad field is all zeros, the station management entity (sta) is requesting a broadcast data transaction. all phys sharing the same management interface must respond to this broadcast request. all 78Q2120 will respond to the broadcast data transaction. additional features led indicators there are seven led pins that can be used to indicate various states of operation of the 78Q2120. there is an led pin that indicates the link is up ( ledl ), others that indicate the 78Q2120 is either tr ansmitting ( ledtx ) or receiving ( ledrx ), one that signals a collision event ( ledcol ), two more that reflect the data rate ( ledbtx and ledbt ), and one that reflects full duplex mode of operation ( ledfdx ). general purpose i/o interface (80 - tqfp onl y) the 78Q2120 80 - pin tqfp has a two pin, bi - directional, general purpose interface that can be used for external control or to monitor external signals. the direction of these pins and data that is either driven or read from these pins is configured via bits mr16.9:6 as detailed in the vendor specific register description of mr16. interrupt pin the 78Q2120 has an interrupt pin (intr) that is asserted whenever any of the eight interrupt bits of mr17.7:0 are set. these interrupt bits can be disabled via mr 17.15:8 interrupt enable bits. the active level of the intr pin is controlled by the interrupt level bit, mr16.14. when the intr pin is not asserted, the pin is held in a high impedance state.
78Q2120 10/100base - tx ethernet transceiver 6 pin description legend type description type description a analog pin i digital input o digital output i/o digital bi - directional pin s supply oz tri - stateable digital output mii (media independ ent interface) pin 64 - pin 80 - pin type description tx_clk 27 33 oz transmit clock : tx_clk is a continuous clock w hich provides a timing reference for the tx_en, tx_er and txd[3:0] signals from the mac. the clock frequency is 25mhz in 100base - tx mode and 2.5mhz in 10base - t mode. this pin is tri - stated in isolate mode. tx_en 28 34 i transmit enable : tx_en is assert ed by the mac to indicate that valid data for transmission is present on the txd[3:0] pins. txd[3:0] 32 - 29 40 - 37 i transmit data : txd[3:0] receives data from the mac for transmission on a nibble basis. this data is captured on the rising edge of tx_clk w hen tx_en is high. tx_er 26 32 i transmit error: tx_er is asserted high to request that an error code - group be transmitted when tx_en is high. in pcs bypass mode this pin becomes the higher - order bit of the transmit 5 - bit code group. crs 34 42 oz carrie r sense: when the 78Q2120 is not in repeater mode, crs is high whenever a non - idle condition exists on either the transmitter or the receiver. in repeater mode, crs is only active when a non - idle condition exists on the receiver. this pin is tri - stated in isolate mode. col 33 41 oz collision: col is asserted high when a collision has been detected on the media. in 10base - t mode col is also used for the sqe test function. this pin is tri - stated in isolate mode. rx_clk 24 30 oz receive clock: rx_clk is a continuous clock which provides a timing reference to the mac for the rx_dv, rx_er and rxd[3:0] signals. the clock frequency is 25mhz in 100base - tx mode and 2.5mhz in 10base - t mode. to reduce power consumption, in 100base - tx mode, the 78Q2120 provides an optional mode enabled through mr16.0 in which rx_clk is held inactive (low) when no receive data is detected. this pin is tri - stated in isolate mode. rx_dv 23 29 oz receive data valid: rx_dv is asserted high to indicate that valid data is present on th e rxd[3:0] pins. in 100base - tx mode, it transitions high with the first nibble of preamble and is pulled low when the last data nibble has been received. in 10base - t mode it transitions high when the start - of - frame delimiter (sfd) is detected. this pin i s tri - stated in isolate mode. rxd[3:0] 19 - 22 23 - 26 oz receive data: received data is provided to the mac via rxd[3:0]. these pins are tri - stated in isolate mode. rx_er 25 31 oz receive error: rx_er is asserted high when an error is detected during frame reception. in pcs bypass mode this pin becomes the higher - order bit of the receive 5 - bit code group. this pin is tri - stated in isolate mode.
78Q2120 10/100base - tx ethernet transceiver 7 mii (continued ) pin 64 - pin 80 - pin type description mdc 18 22 i management data cloc k: mdc is the clock used f or transferring data via the mdio pin. mdio 17 21 i/o management data inpu t/output: md io is a bi - directional port used to access management registers within the 78Q2120. this pin requires an external pull - up resistor as specified in ieee - 802.3. phy addre ss phyad[4:0] 12 - 16 14 - 18 i phy address : allows 31 configurable phy addresses. the 78Q2120 always responds to data transactions via the mii interface when the phyad bits are all zero independent of the logic levels of the phyad pins. pma (physical media attachment) interfac e pcsbp 64 1 i pcs bypass : when high, the 100base - tx pcs is bypassed, as well as the scrambler and descrambler functions. scrambled 5 - bit code groups for transmission are applied to the tx_er, txd[3:0] pins and received on the rx_er, rx d[3:0] pins. the rx_dv and tx_en signals are not valid in this mode. pcs bypass mode is only valid when 100base - tx is enabled. this mode can also be entered with mr16.1. control and status rst 6 8 i reset : when pulled low the pin resets the chip. the rese t pulse must be long enough to guarantee stabilization of vcc and startup of the oscillator. there are 2 other ways to reset the chip: i) through the internal power - on - reset (activated when the chip is being powered up) ii) through the mii register bit (mr 0.1 5) pwrdn 7 9 i power - down : the 78Q2120 may be placed in a low power consumption state by setting this signal to logic high. while in power - down state, the 78Q2120 still responds to management transactions. the same power - down state can also be achieved th rough the pwrdn bit in the mii register (mr0.11). iso 2 3 i isolate : when set to logic one, the 78Q2120 will present a high impedance on its mii output pins. this allows for multiple chips to be attached to the same mii interface. when the 78Q2120 is isol ated, it still responds to management transactions. the same high impedance state can also be achieved through the iso bit in the mii register (mr0.10). isodef 1 2 i isolate default : this pin determines the power - up/reset default of the iso bit (mr0.10). if it is connected to vdd (gnd), iso bit will have a default value of 1 (0). when this signal is tied to vdd, it allows multiple chips to be connected to the same mii interface.
78Q2120 10/100base - tx ethernet transceiver 8 control and status (continued) pin 64 - pin 80 - pin type description anega 47 56 i auto - negotiation abi lity : strapped to logic high to allow auto - negotiation function. when strapped to logic low, auto - negotiation logic is disabled and manual technology selection is done through tech[2:0]. this pin is reflected as anega bit (mr1.3). tech[2:0] 44 - 46 53 - 55 i technology ability/s elect : tech[2:0] sets the technology ability of the chip which is reflected in mr0.13,8 mr1.14:11 and mr4.12:5. tech[2:0] technology ability 000 advertise no technology capability; however, parallel detect from the link partner will establish the link speed. 111 both 10base - t and 100base - tx, both half and full duplex 001 10base - t, half duplex 010 100base - tx, half duplex 011 both 10base - t and 100base - tx,half duplex 100 none 101 10base - t both half and full duplex 11 0 100base - tx both half and full duplex rptr 50 61 i repeater mode: when pulled high, this pin puts the chip into repeater mode. in this mode, full duplex is prohibited, crs responds to receive activity only and, in 10base - t mode, the sqe test function is disabled. this mode can also be entered with mr16.15. mdi (media dependent interface) txop, txon 61, 62 77,78 a transmit output positive/neg ative : transmitter outputs for both 10base - t and 100base - tx. rxip, rxin 52, 51 64,63 a receive input positi ve/nega tive : receiver inputs for both 10base - t and 100base - tx. led indicators the led pins use standard logic drivers. they output a logic low when the led is meant to be on and a logic high when it is meant to be off. the led should be connected in series with a resistor between the output pin and the power supply. ledl 40 48 o led link : on for link up. ledtx 39 47 o led transmit : on when there is a transmission (normally off). ledrx 38 46 o led receive : on when there is a reception (normally off). ledcol 37 45 o led collision : in half duplex mode, this is a collision indicator and turns - on when a collision occurs. in full duplex mode, this led is held off. ledbtx 36 44 o led 100base - tx: on for 100base - tx connection and off for other connections. ledbtx is off during auto - negotiation. ledbt 48 57 o led 10base - t: on for 10base - t connection and off for other connections. ledbt is off during auto - negotiation. ledfdx 49 58 o led full duplex: on when in full duplex mode and off when in half duplex mode.
78Q2120 10/100base - tx ethernet transceiver 9 osc illator/clock name 64 - pin 80 - pin type description ckin 4 5 i clock input: connects to a 25 mhz clock source. this pin should be held low when xtlp and xtln are being used as the 25 mhz clock source. xtlp, xtln 59, 58 75,74 a crystal pins: should be conn ected to a 25 mhz crystal. when ckin is being used as the 25 mhz clock source, these pins should be connected together. miscellaneous pins gpio0 - 19 i/o general purpose i/o pin: this is an i/o pin which is configurable as an input or an output via manage ment interface. a value of one in bit mr16.6 configures gpio0 as an input, and a zero configures it as an output. the logic level of the gpio0 pin is reflected in mr16.7. this pin has a weak internal pull - down to prevent it from floating when configured as an input (it is configured as an input by default). gpio1 - 20 i/o general purpose i/o pin: this is an i/o pin which is configurable as an input or an output via the management interface. a value of one in bit mr16.8 configures gpio1 as an input, and a zero configures it as an output. the logic level of the gpio1 pin is reflected in mr16.9. this pin has a weak internal pull - down to prevent it from floating when configured as an input (it is configured as an input by default). intr 35 43 oz interrupt pin : this pin is used to signal an interrupt to the media access controller. the pin is held in the high impedance state when an interrupt is not indicated. the pin will be forced high or low to signal an interrupt depending upon the value of the intr_level b it (mr16.14). the events which trigger an interrupt can be programmed via the interrupt control register located at address mr17. power supply v cc 8, 11, 41, 43, 57, 63 10,13, 27,36, 49, 52, 59, 60, 73, 79 80 s supply voltage : two supply ranges are suppor ted: 5v 0.5v, or 3.3v 0.3v. gnd 3, 5, 9, 10, 42, 53, 55, 60 4,7, 11,12, 28, 35, 50, 51, 65, 71, 76 s ground reference pin ribb 56 72 a bias current setting resistor: to be tied to an exter nal resistor which is also connected to pin 70. this resistor should be placed as close as possible to the package pin. see figure 1 for suggested value. ribb_ret 54 70 a bias current setting resistor return pin : to be connected to external ribb resistor .
78Q2120 10/100base - tx ethernet transceiver 10 register description the 78Q2120 implements ten 16 - bit registers which are accessible via the mdio and mdc pins. the supported registers are shown below. unsupported registers will be read as all zeros. all of the registers respond to the broadcast add ress, phyad value 00000. the mii management 16 - bit register set implemented in the 78Q2120 is as follows: address symbol name reset value (hex) 0 mr0 control (3100) 1 mr1 status (7809) 2 mr2 phy identifier 1 0300 3 mr3 phy identifier 2 (e542) 4 mr4 au to - negotiation advertisement (01e1) 5 mr5 auto - negotiation link partner ability 0000 6 mr6 auto - negotiation expansion 0000 7 mr7 (not implemented, read as zero) 0000 8 - 15 mr8 - 15 (reserved, read as zero) 0000 16 mr16 vendor specific 0540 17 mr17 inter rupt control/status register 0000 18 mr18 diagnostic register (0000) note: mr 3.3:0 contains revision specific data. legend type description type description r readable by management w write - able by management rc cleared on a read operation sc self cle aring, write - able 0/1 default value upon power - up or reset (0/1) default value dependent on pin setting. the value in brackets indicates typical case.
78Q2120 10/100base - tx ethernet transceiver 11 mr0 - control regist er bit symbol type description 0.15 reset r, w, 0, sc reset: setting this bit to logic one resets the entire 78Q2120. this bit is self clearing. 0.14 loopbk r, w, 0 loopback: when this bit is set, no transmission of data on the network medium occurs and any receive data on the network medium is ignored. by default, the loopback signal path will encompass as much of the 78Q2120 circuitry as possible. 0.13 speedsl r, w, (1) speed selection : this bit determines the speed of operation of the 78Q2120. a logic one indicates 100base - tx operation and a logic zero indicates 10base - t. when aut o - negotiation is enabled, this bit will have no effect on the 78Q2120. at reset, this bit reflects the highest operating speed allowed by the tech [2:0] pins. the mii can write to this bit, but the bit will change value only if the new value is allowed b y the tech [2:0] pins. 0.12 anegen r, w, (1) auto - negotiation ena ble : the auto - negotiation process is enabled by setting this bit to a logic one. this bit can only be set to logic one if the anega pin is a logic one and will default to a logic one upon r eset in this case. if this bit is cleared to logic zero, manual speed and duplex mode selection is accomplished through bits 0.8 (duplex) and 0.13 (speedsl) of the configuration register or the tech[2:0] pins according to the table shown in the section de scribing the tech[2:0] pins. if the anega pin is brought from zero to one and reset is not asserted, this bit will remain at zero until a one is written. 0.11 pwrdn r, w, 0 power - down : the 78Q2120 may be placed in a low power consumption state by setting this bit to logic one. while in power - down state, the 78Q2120 still responds to management transactions. the power - down state can also be achieved by setting pwrdn pin high. 0.10 iso r, w, (0) isolate : when set, the 78Q2120 will present a high impedance on its mii output pins. this allows for multiple phy to be attached to the same mii interface. when the 78Q2120 is isolated, it stills responds to management transactions. the default value of this bit depends on the isodef pin. when isodef pin is tied hi gh the iso bit defaults to high. when isodef pin is tied low, the iso bit defaults to low. the same high impedance state can be achieved through the iso pin. 0.9 raneg r, w, 0, sc restart auto - negotia tion : normally, the auto - negotiation process is start ed at power - up. the process can be restarted by setting this bit to logic one. this bit is self clearing.
78Q2120 10/100base - tx ethernet transceiver 12 mr0 - control regist er (continued ) bit symbol type description 0.8 duplex r, w, (1) duplex mode : this bit determines whether the 78Q2120 supports f ull duplex or half duplex. a logic one indicates full duplex operation and a logic zero indicates half duplex. when auto - negotiation is enabled, this bit will have no effect on the 78Q2120. at reset, this bit reflects the highest operating mode allowed b y the tech [2:0] pins. the mii can write to this bit, but the bit will change value only if the new value is allowed by the tech pins. 0.7 colt r, w, 0 collision test : when this bit is set to one, the 78Q2120 will assert the col signal in response to the assertion of tx_en signal. collision test is disabled in pcs bypass mode. collision test is enabled regardless of the duplex mode of operation. 0.6:0 rsvd r, 0 reserved mr1 - status registe r bits 1.15 through 1.11 reflect the ability of the 78Q2120 as configured by the tech[2:0] pins they do not reflect any ability changes made via the mii management interface to bits 0.13 (speedsl), 0.12 (anegen) and 0.8 (duplex). bit symbol type description 1.15 100t4 r, 0 100base - t4 ability : this bit is permanentl y held at logic zero to indicate that the 78Q2120 is not capable of 100base - t4. 1.14 100x_f r, (1) 100base - tx full dupl ex ability : (0 = not able, 1 = able) 1.13 100x_h r, (1) 100base - tx half duplex abil ity : (0 = not able, 1 = able) 1.12 10t_f r, (1) 10b ase - t full duplex ab ility : (0 = not able, 1 = able) 1.11 10t_h r, (1) 10base - t half duplex ability : (0 = not able, 1 = able) 1.10:6 rsvd r, 0 reserved 1.5 anegc r, 0 auto - negotiation com plete : a logic one indicates a) that the auto - negotiation process h as completed, b) that the contents of registers mr4, 5, and 6 are valid, and c) that a highest common denominator rate and mode have been found. 1.4 rfault r, 0, rc remote fault : a logic one indicates that a remote fault condition has been detected. it r emains set until it is cleared. this bit can only be cleared by reading this register (mr1) via the management interface. 1.3 anega r, (1) auto - negotiation abi lity : this bit, when set, indicates the ability to perform auto - negotiation. the value of this b it is determined by the anega pin. 1.2 link r, 0 link status : a logic one indicates that a valid link has been established. if the link status should transition from an ok status to a not - ok status, this bit will become cleared and remain cleared until it is read. 1.1 jab r, 0, rc jabber detect: i n 10base - t mode, this bit is set during a jabber event. after a jabber event it remains set until cleared by a read operation. 1.0 extd r, 1 extended capability : this bit is permanently set to logic one to ind icate that the 78Q2120 provides an extended register set (mr2 and beyond).
78Q2120 10/100base - tx ethernet transceiver 13 mr2, 3 - phy identif ier register 2.15:0 oui r, 0300h organizationally unique identifier: this value is 00 - c0 - 39 for tdk semiconductor corporation. this translates to a value of 30 0h for this register. 3.15:10 oui r, 111001 organizationally unique identifier: remaining 6 bits of the oui. 3.9:4 mn r, 010100 model number: the last 2 digits of the model number 78Q2120 is encoded into the 6 bits. (20d = 14h) 3.3:0 rn r revision num ber: for example, a value of 0010 corresponds to the second version of the silicon. mr4 - auto - negotiati on advertisement reg ister bit symbol type description 4.15 np r,0 next page : not supported; permanently tied to logic zero. 4.14 rsvd r,0 reserved: this bit is permanently set to logic 0. 4.13 rf r, w, 0 remote fault : when internally set to logic one, the mii management interface indicates to the link partner a remote fault condition. 4.12:5 taf r, w, (0fh) technology ability f ield : the default valu e of this field is dependent upon mr1.15:11 bits. this field can be overwritten by management to auto - negotiate to an alternate common technology. writing to this register has no effect until auto - negotiation is enabled. 4.12:10 a7:5 r, 0 reserved for fut ure technology. 4.9 a4 r, 0 100base - t4: the 78Q2120 does support 100base - t4. 4.8 a3 r, w, (1) 100base - tx full duplex : the default value of this bit follows mr1.14 bit. when the default is zero, this bit set by the management. 4.7 a2 r, w, (1) 100base - tx :the default value of this bit follows mr 1.13 bit. when the default is zero, this bit cannot be set by the management. 4.6 a1 r, w, (1) 10base - t full duplex : the default value of this bit follows mr1.12 bit. when the default is zero, this bit cannot be s et by the management. 4.5 a0 r, w, (1) 10base - t : the default value of this bit follows mr1.11 bit. when the default is zero, this bit cannot be set by the management. 4.4:0 s4:0 r, 00001 selector field : hard coded with the value of 00001 for ieee - 802.3.
78Q2120 10/100base - tx ethernet transceiver 14 register description (continued) mr5 - auto - negotiati on link partner abil ity register bit symbol type description 5.15 np r, 0 next page : when set, it indicates that the link partner wishes to engage in next page exchange. 5.14 ack r, 0 acknowledge: w hen set, it indicates that the link partner has successfully received at least 3 consecutive and consistent flp bursts. 5.13 rf r, 0 remote fault: when set, it indicates that the link partner has a fault. 5.12:5 a7:0 r, 0 technology ability f ield : this f ield contains the technology ability of the link partner. the bit definition is the same as mr4.12:5. 5.4:0 s4:0 r, 00000 selector field : this field contains the type of message sent by the link partner. for ieee - 802.3 compliant link partner transceiver, this field should be 00001. mr6 - auto - negotiati on expansion registe r 6.15:5 rsvd r, 0 reserved 6.4 pdf r, 0, rc parallel detection f ault: when set, it indicates that more than one technology was detected during link up. this bit is cleared when read. 6.3 lpnpa r, 0 link partner next pa ge able : when set, it indicates that the link partner supports the next page function. 6.2 npa r, 0 next page able : permanently tied to logic zero since the 78Q2120 does not support next page function. 6.1 prx r, 0, rc page received: set when a properly matched link code word has been received into the auto - negotiation link partner. this bit is cleared when read. 6.0 lpanega r, 0 link partner auto - ne gotiation able : when set it indicates that the link partner is abl e to participate in the auto - negotiation function.
78Q2120 10/100base - tx ethernet transceiver 15 mr16 - vendor specif ic register bit symbol type description 16.15 rptr r, w, (0) repeater mode: when set, this bit puts the chip into repeater mode. in this mode, full duplex is prohibited, crs respond s to receive activity only and, in 10base - t mode, the sqe test function is disabled. 16.14 int level r, w, 0 when this bit is a zero, the intr pin is forced low to signal an interrupt. setting this bit causes the intr pin to be forced high to signal an in terrupt. 16.13 rsvd r, 0 reserved 16.12 txhim r, w, 0 transmit high impedance: when this bit is set, the transmitter utp drivers are in a high impedance state and txclk is tri - stated. the receive circuitry remains fully functional. only a reset condition will automatically clear this bit. 16.11 sqe t est inhibit r, w, 0 setting this bit disables 10base - t sqe testing. by default, when this bit is a zero, the sqe test is performed by generating a col pulse following the completion of a packet transmission. 16.10 10bt natural loopback r, w, 0 setting this bit causes transmitted data on txd to be automatically looped back to the rxd receive signals when 10base - t mode is enabled. 16.9 gpio1_dat r, w, 0 general purpose i/o 1 data bit : when the gpio_dir is set, this bit reflects the value of the gpio1 pin. when the gpio1_dir is reset, the value of this bit is driven onto the gpio1 pin. (80 - pin tqfp only) 16.8 gpio1_dir r, w, 1 general purpose i/o 1 direction bit: setting this bit configures the gpio1 pin as an input. resetting configures gpoi_1 as an output. (80 - pin tqfp only) 16.7 gpio0_dat r, w, 0 general purpose i/o 0 data bit : when the gpio0_dir is set, this bit reflects the value of the gpio0 pin. when the gpio0_dir is reset, the value of this bit is drive n onto the gpio0 pin. (80 - pin tqfp only) 16.6 gpio0_dir r, w, 1 general purpose i/o 0 direction bit: setting this bit configures the gpio0 pin as an input. resetting it configures gpio0 as an output. (80 - pin tqfp only) 16.5 apol r, w, 0 auto polarity : du ring auto - negotiation and 10base - t mode, the 78Q2120 is able to automatically invert the received signal - both the manchester data and link pulses - if necessary. setting this bit disables this feature. 16.4 rvspol r, (w), 0 reverse polarity : the reverse polarity is detected either through 8 inverted 10base - t link pulses (nlp) or through one burst of inverted fast link pulses (flp). when the reverse polarity is detected, the 78Q2120 will invert the receive data path and set this bit to logic one if the fe ature is not disabled. if apol is a logic 1, then this bit is write - able. setting this bit forces the polarity to be reversed. 16.3:2 rsvd r,w,0 reserved . must be zero.
78Q2120 10/100base - tx ethernet transceiver 16 mr16 - vendor specif ic register (continued) bit symbol type description 16.1 pc sbp r,w,0 pcs bypass : when set, the 100base - tx pcs is bypassed, as are the scrambler and descrambler functions. scrambled 5 - bit code groups for transmission are applied to the tx_er, txd[3:0] pins and received on the rx_er, rxd[3:0] pins. the rx_dv and tx_ en signals are not valid in this mode. pcsbp mode is only valid when 100base - tx is enabled. 16.0 rxcc r,w,0 receive clock contro l : when set, the rx_clk signal will be held in logic low (only in 100base - tx mode) when there is no data being received (to s ave power). the rx_clk signal will restart 1 clock cycle before the assertion of rx_dv and be shut off 64 clock cycles after rx_dv goes low. rxcc is disabled when loopback mode is enabled (mr0.14 is high). this bit should be kept at logic zero when the chip is in pcs bypass mode. mr17 - interrupt con trol/status register the interrupt control/status register provides the means for controlling and observing the events which trigger an interrupt on the intr pin. this register can also be used in a polling mode via the mii serial interface as a means to observe key events within the phy via one register address. these bits are cleared after the register is read. bits 8 - 15 of this register, when set to logic one, enable their corresponding bit in the lower b yte to signal an interrupt on the intr pin. the level of this interrupt can be set via mr16.14. 17.15 jabber ie r, w, 0 jabber interrupt ena ble bit 17.14 rxer ie r, w, 0 receive error interr upt enable bit 17.13 prx ie r, w, 0 page received interr upt enab le bit 17.12 pfd ie r, w, 0 parallel detect faul t interrupt enable b it 17.11 lp - ac k ie r, w, 0 link partner acknowl edge interrupt enabl e bit 17.10 ls - chg ie r, w, 0 link status change i nterrupt enable bit 17.9 rfault ie r, w, 0 remote fault interru pt enable bit 17.8 aneg - comp ie r, w, 0 auto - negotiation com plete interrupt enab le bit 17.7 jabber int rc, 0 jabber interrupt: this bit is set when a jabber event is indicated by the 10base - t circuitry. 17.6 rxer int rc, 0 receive error interr upt : this bit is set when the rx_er signal transitions high. 17.5 prx int rc, 0 page receive interru pt: this bit is set when a new page has been received from the link partner during auto - negotiation. 17.4 pdf int rc, 0 parallel detect faul t interrupt : this bit is s et by the auto - negotiation logic when a parallel detect fault condition is indicated. 17.3 lp - ack int rc, 0 link partner acknowl edge interrupt: this bit is set by the auto - negotiation logic when flp bursts are received with the acknowledge bit set. 17.2 ls - chg int rc, 0 link status change i nterrupt: this bit is set when the link transitions from an ok status to a fail status or vice versa. 17.1 rfault int rc, 0 remote fault interru pt: this bit is set when a remote fault condition has been indicated by th e link partner. 17.0 aneg - comp int rc, 0 auto - negotiation com plete interrupt: this bit is set by the auto - negotiation logic upon successful completion of auto - negotiation.
78Q2120 10/100base - tx ethernet transceiver 17 mr18 - diagnostic re gister bit symbol type description 18.15:13 rsvd r, 0 reserve d 18.12 anegf r,0,rc auto - negotiation fail: this bit is set when auto - negotiation completes and no common technology was found. it remains set until read. 18.11 dplx r, 0 duplex: this bit indicates the result of the auto - negotiation for duplex arbitratio n. if set it indicates that full - duplex was the highest common denominator. if clear it indicates that half - duplex was the highest common denominator. 18.10 rate r, 0 rate: this bit indicates the result of the auto - negotiation for data rate arbitration. i f set it indicates that 100base - tx was the highest common denominator. if clear it indicates that 10base - t was the highest common denominator. 18.9 rx - pass r, 0 receive pass: in 10base - t mode, this bit indicates that manchester data has been detected. in 100base - tx mode, it indicates that a valid received signal has been detected (but not necessarily locked on to). 18.8 rx - lock r, 0 receive lock: indicates that the receive pll has locked onto the received signal for the selected speed of operation (10ba se - t or 100base - tx). this bit is cleared whenever a cycle - slip occurs, and will remain cleared until it is read. 18.7:0 rsvd r, w, 0 reserved. must be zero .
78Q2120 10/100base - tx ethernet transceiver 18 electrical specifica tions absolute maximum rat ings operation above maximum rating may permane ntly damage the device. parameter rating dc supply voltage 7 vdc storage temperature - 65 to 150 c pin voltage - 0.3 to (vcc+0.3) vdc pin current 100 ma recommended operatin g conditions unl ess otherwise noted all specifications are valid over these temperatures and supply voltage ranges: dc voltage supply, vcc 3.3 v 0.3v, 5 v 0.5v vdc ambient operating temperature, ta 0 - 70 c dc charateristics: parameter symbol conditions min nom max unit supply current i cc v cc = 3.3v; auto - negotiation 10bt (idle) 10bt (normal activity) 100btx transmit high impedance 25 25 85 95 30 30 30 100 115 35 ma supply current i cc v cc = 5.0v; auto - negotiation 10bt (idle) 10bt (normal activity) 100btx transmit high impedance 30 30 90 105 35 35 35 115 135 40 ma supply current i cc powerdown mode 500 800 m a
78Q2120 10/100base - tx ethernet transceiver 19 digital input characteristics pins of type i, i/o characteristics symbol conditions min nom max unit ttl input voltage low v il 0.8 v ttl input voltage high v ih 2.0 v ttl input current i il , i ih v cc = 5.5v - 10 +10 m a input capaci tance c in 10 pf digital output chara cteristics pins of type o, oz output voltage high v oh 4.5v v cc 5.5v i oh = 4.0ma v cc - 0.6 v output voltage low v ol 4.5v v cc 5.5v i ol = 4.0ma 0.4 v output transition time between v ol and v oh t t 4.5v v cc 5.5v i oh , i ol = 4.0ma 5 ns output voltage high v oh 3.0v v cc 3.6v i oh = 2.0ma v cc - 0.4 v output voltage low v ol 3.0v v cc 3.6v i ol = 2.0ma 0.4 v output transition time between v ol and v oh t t 3.0v v cc 3.6v i oh , i ol = 2.0ma 5 ns
78Q2120 10/100base - tx ethernet transceiver 20 electrical specifica tions (continued) digital timing chara cteristics transmit inputs to the 78Q2120 mii transmit interfa ce characteristics sy mbol conditions min nom max unit setup time: tx_clk to txd[3:0], tx_en, tx_er tx su 15 ns hold time: tx_clk to txd[3:0], tx_en, tx_er tx hd 0 ns ckin - to - tx_clk delay t ckin 20 35 ns tx_clk duty - cycle 40 60 % receive outputs from the 78q21 20 mii receive interfac e characteristics symbol conditions min nom max unit receive output delay: rx_clk to rxd[3:0], rx_dv, rx_er rx dly 10 30 ns rx_clk duty - cycle 40 60 %
78Q2120 10/100base - tx ethernet transceiver 21 mdio as an input to the 78Q2120 mdio interface input timing characteris tics symbol conditions min nom max unit setup time: mdc to mdio mio su 10 ns hold time: mdc to mdio mio hd 0 ns max frequency: mdc f max 25 mhz mdio as an output from the 78Q2120 mdio interface outpu t timing characteristics symbol condition s min nom max unit mdc to mdio data delay mc2d 30 ns mdio output from high z to driven after mdc mcz2d 30 ns mdio output from driven to high z after mdc mcd2z 30 ns
78Q2120 10/100base - tx ethernet transceiver 22 electrical specifica tions (continued) mdio interface output timing
78Q2120 10/100base - tx ethernet transceiver 23 100bas e - tx system timing system timing requirements for 100base - tx operation are listed in table 24 - 2 of clause 24 of ieee 802.3. parameter condition nom unit tx_en sampled to first bit of ?j? on mdi output 12 bt first bit of ?j? on mdi input to crs assert 1 5 bt first bit of ?t? on mdi input to crs de - assert 23 bt first bit of ?j? on mdi input to col assert 16 bt first bit of ?t? on mdi input to col de - assert 24 bt tx_en sampled to crs assert rptr = low 4 bt tx_en sampled to crs de - assert rptr = low 4 bt 10base - t system timing parameter condition min nom max unit tx_en (mii) to td delay 6 bt rd to rxdat (mii) delay 6 bt collision delay 9 bt sqe test wait 1 m s sqe test duration 1 m s jabber on - time* 20 150 ms jabber off - time* 250 750 ms * guarantee by design. the specifications in the above table are not tested during production test. they are included for information only.
78Q2120 10/100base - tx ethernet transceiver 24 electrical specifica tions (continued) an alog electrical char acteristics 100base - tx transmitter parameter condition min nom max unit *peak output amplitude, vp+, vp - best - fit over 14 bit times; 0.5 db transformer loss 950 1050 mv output amplitude symmetry | vp +| | vp - | 0.98 1.02 output overshoot percent of vp+, vp - 5 % rise/fall time, tr, tf 10 - 90% of vp+, vp - 3 5 ns rise/fall time imbalance | tr - tf | 500 ps duty cycle distortion deviation from best - fit time - grid; 010101... sequence 250 ps 100base - tx transmitter the specifications in the following table are not tested during production test. they are included for information only. parameter condition min max unit return loss 2 < f < 30 mhz 30 < f < 60 mhz 60 < f < 80 mhz 16 16 20 30 - ? ? ? ? log f mhz 10 db open circuit inductance - 8 < iin < 8 ma 350 m h jitter scrambled idle 1.4 ns * measured at the line side of the transformer. test conditions: transformer p/n: tla - 6t103 line termination: 100 w 1% ribb: 9.76k 1% @3.3v
78Q2120 10/100base - tx ethernet transceiver 25 100base - tx transmitt er the specifications in the following table are not tested during production test. they are included for information only. parameter condition min nom max unit signal detect assertion threshold (pk - pk) 6 00 900 1000 mv signal detect de - assertion threshold (pk - pk) 300 350 400 mv differential input resistance 20 k w pll locking time 5 m s jitter tolerance (pk - pk) 4 ns baseline wander t racking - 75 +75 % signal detect assertion time 200 m s signal detect de - assertion time 1.4 m s 10base - t transmitter the manchester - encoded data pulses, the link pulse and the start - of - idle pulse are tested against the templates and using the procedures found in clause 14 of ieee 802.3. parameter condition min nom max unit **peak differential output signal all data patterns 2.2 2.8 v link pulse width 100 ns start - of - idle pulse wid th 300 350 ns ** measured at the line side of the transformer. test conditions: transformer p/n: tla - 6t103 line termination: 100 w 1% ribb: 9.76k 1% @3.3v
78Q2120 10/100base - tx ethernet transceiver 26 10base - t transmitter the specifications in the following table are not tested during production test. they are included for information only. output return loss 15 db harmonic content any harmonic; db below fundamental; a ll ones data 27 db output impedance balance 1 mhz < freq < 20 mhz 29 17 10 - ? ? ? ? log f db peak common - mode output voltage 50 mv common - mode rejection 15 v pk , 10.1 mhz sine wave applied to transmitter common - mode. all data sequences. 100 mv co mmon - mode rejection jitter 15 v pk , 10.1 mhz sine wave applied to transmitter common - mode. all data sequences. 1 ns 10base - t receiver parameter condition min nom max unit pll locking time 1.8 m s jitter tolerance (pk - pk ) 32 ns input squelched threshold 600 900 1000 mv input un - squelch threshold 300 350 400 mv 10base - t receiver the specifications in the following table are not tested during production test. they are included for information only. bit error ratio 10 - 10 differential input resistance 20 k w common - mode rejection square wave 0 < f < 500 khz 25 v
78Q2120 10/100base - tx ethernet transceiver 27 figure1 - typical circuit application 64 - pin tqfp (jedec lqfp) and 64 - p in qfp devices
78Q2120 10/100base - tx ethernet transceiver 28 figure1 - typical circuit application 80 - pin tqfp (jedec lqfp) device
78Q2120 10/100base - tx ethernet transceiver 29 isolation transforme rs two simple 1:1 isolation transformers are all that are required at the line interface, but transformers with integrated common - mode choke are recommended for exceeding fcc requirements. this table gives the recommended line transformer characteristics: name value condition turns ratio 1 ct : 1 ct 5% open - circuit inductance 350 uh (min) @ 10 mv, 10 khz leakage inductance 0.40 uh (max) @ 1 mhz (min) inter - winding capacitance 12 pf (max) d.c. resistance 0.9 w (max) insertion loss 1.1 db (typ ) 0 - 100 mhz hipot 1500 vrms note: the 100base - tx amplitude specifications assume a transformer loss of 0.5 db. for the transmit line transformer, insertion loss up to 1.3 db can be compensated by increasing the line drive current by means of reducin g the ribb resistor value. reference crystal if the internal crystal oscillator is to be used, a crystal with the following characteristics should be chosen: name value units frequency 25.00000 mhz load capacitance 15 pf frequency tolerance 50 ppm aging 2 ppm/yr temperature stability ( 0 - 70 o c) 5 ppm oscillation mode parallel resonance, fundamental mode parameters at 25 o c 2 o c ; drive level = 0.5 mw shunt capacitance (max) 8 pf motional capacitance (min) 10 ff series resistance (max) 25 w spurious response (max) > 5 db below main within 500 khz
78Q2120 10/100base - tx ethernet transceiver 30 mechanical specifications 64 - qfp 64 - tqfp
78Q2120 10/100base - tx ethernet transceiver 31 80 - tqfp (jedec lqfp)
78Q2120 10/100base - tx ethernet transceiver 32 package pin designations (top view) 64 - lead tqfp (jedec lqfp) and 64 qfp caution: use handling procedures necessary for a static sensitive component
78Q2120 10/100base - tx ethernet transceiver 33 package pin designations (top view) 80 - lead tqfp (jedec lqfp) ordering information part description order n umber package mark 78Q2120 - cgt 80 - pin plastic tqfp 78Q2120 - cgt 78Q2120 - cgt 78Q2120 - 64cg 64 - pin plastic qfp 78Q2120 - 64cg 78Q2120 - 64cg 78Q2120 - 64cgt 64 - pin plastic tqfp 78Q2120 - 64t 78Q2120 - 64t no responsibility is assumed b y tdk semiconductor corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. no license is granted under any patents, patent rights or trademarks of tdk semiconductor c orporation, and the company reserves the right to make changes in specifications at any time without notice. accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. tdk semiconductor corporation, 2642 michelle drive, tustin, ca 92780 - 7019, (714) 508 - 8800, fax: (714) 508 - 8877 tdk semiconductor corporation 04/20/00 - rev. i caution: use handling procedures necessary for a static sensitive component

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